/****************************************************************************
 *                                                                                    
 * Copyright (c) 2005 - 2005 Winbond Electronics Corp. All rights reserved.           
 *                                                                                    
 ***************************************************************************/
 
/****************************************************************************
 * 
 * FILENAME
 *     DmacReg.h
 *
 * VERSION
 *     1.0
 *
 * DESCRIPTION
 *     The register definitions for 910 DMA Controller.
 **************************************************************************/

#ifndef _LCDCREG_H_
#define _LCDCREG_H_

/* I/O Base */
#define	  DMAC_BASE_ADDRRESS       0xB000C800  /* Base address of DMA controller */

/************************************************************************** 
   910 DMA Controller Register Sets 
**************************************************************************/
#define	  DMAC_CSR    (DMAC_BASE_ADDRRESS + 0x000)   /* DMAC Control Register */
#define	  DMAC_SAR1   (DMAC_BASE_ADDRRESS + 0x004)   /* DMAC Transfer Starting Address Register */
#define	  DMAC_SAR2   (DMAC_BASE_ADDRRESS + 0x008)   /* DMAC Transfer Starting Address Register */
#define	  DMAC_BCR   (DMAC_BASE_ADDRRESS + 0x00C)   /* DMAC Transfer Byte Count Register */
#define	  DMAC_IER   (DMAC_BASE_ADDRRESS + 0x010)   /* DMAC Interrupt Enable Register */
#define	  DMAC_ISR   (DMAC_BASE_ADDRRESS + 0x014)   /* DMAC Interrupt Status Register */
#define	  DMAC_BIST  (DMAC_BASE_ADDRRESS + 0x018)   /* DMAC BIST Register */

#define   DMAC_SHAREBUFFERSTARTADDRESS0   (DMAC_BASE_ADDRRESS + 0x200)   /* Starting address of Shared Buffer 0 */
#define   DMAC_SHAREBUFFERSTARTADDRESS1   (DMAC_BASE_ADDRRESS + 0x400)   /* Starting address of Shared Buffer 1 */

/************************************************************************** 
   910 DMA Controller Register Sets
   - Bits Definition
**************************************************************************/
#define   DMAC_CR_RDSEL_DMAC_READ_BUFFER0         0x00000000   /* DMAC can read buffer 0 */
#define   DMAC_CR_RDSEL_ATAPI_READ_BUFFER0        0x00000100   /* ATAPI can read buffer 0 */
#define   DMAC_CR_RDSEL_FMI_READ_BUFFER0          0x00000200   /* FMI can read buffer 0 */
#define   DMAC_CR_RDSEL_DMAC_READ_BUFFER0AND1     0x00000300   /* DMAC can read buffer 0 and buffer 1 */
#define   DMAC_CR_RDSEL_DMAC_READ_BUFFER1         0x00000400   /* DMAC can read buffer 1 */
#define   DMAC_CR_RDSEL_ATAPI_READ_BUFFER1        0x00000500   /* ATAPI can read buffer 1 */
#define   DMAC_CR_RDSEL_FMI_READ_BUFFER1          0x00000600   /* FMI can read buffer 1 */
#define   DMAC_CR_RDSEL_FMI_READ_BUFFER0AND1      0x00000700   /* ATAPI can read buffer 0 and buffer 1 */
#define   DMAC_CR_WRSEL_DMAC_WRITE_BUFFER0        0x00000000   /* DMAC can write buffer 0 */
#define   DMAC_CR_WRSEL_ATAPI_WRITE_BUFFER0       0x00000010   /* ATAPI can write buffer 0 */
#define   DMAC_CR_WRSEL_FMI_WRITE_BUFFER0         0x00000020   /* FMI can write buffer 0 */
#define   DMAC_CR_WRSEL_DMAC_WRITE_BUFFER0AND1    0x00000030   /* DMAC can write buffer 0 and buffer 1 */
#define   DMAC_CR_WRSEL_DMAC_WRITE_BUFFER1        0x00000040   /* DMAC can write buffer 1 */
#define   DMAC_CR_WRSEL_ATAPI_WRITE_BUFFER1       0x00000050   /* ATAPI can write buffer 1 */
#define   DMAC_CR_WRSEL_FMI_WRITE_BUFFER1         0x00000060   /* FMI can write buffer 1 */
#define   DMAC_CR_WRSEL_ATAPI_WRITE_BUFFER0AND1   0x00000070   /* ATAPI can write buffer 0 and buffer 1 */

#define   DMAC_CR_WR_READ                         0x00000000   /* Read DMA transfer from SDRAM to internal FIFO */
#define   DMAC_CR_WR_WRITE                        0x00000008   /* Write DMA transfer from internal FIFO to SDRAM */
#define   DMAC_CR_SWRST                           0x00000002   /* Software Reset */
#define   DMAC_CR_DMACEN                          0x00000001   /* DMAC Function Enable */
#define   DMAC_CR_SG_EN                           0x00000004    





#endif /* End of _LCDCREG_H_ */